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Resettable delay line segments amongst a resettable delay line section 210-one affiliated with a minimum hold off time along with a resettable delay line section 210-N connected with a greatest delay time are Every single connected to discretely expanding hold off occasions. An evaluate circuit 240 is triggered by a clock CLK and uses the plurality of delayed monotone indicators to detect a voltage fault.
32. The apparatus for detecting voltage tampering as described in assert thirty, wherein the implies for triggering the implies for evaluating takes advantage of a clock edge at an conclusion in the Assess time period to induce the signifies for analyzing.
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two. The tactic for detecting clock tampering as outlined in assert 1, additional comprising: resetting the resettable hold off line segments through a reset period of time, whereby the reset period of time is before the clock Examine period of time.
usually means for delaying the monotone sign to create a plurality of delayed monotone alerts acquiring discretely escalating hold off moments involving a minimum hold off time plus a most hold off time and every in the plurality of delayed monotone indicators acquiring either a a single or a zero logic price;
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nine. The equipment for detecting clock tampering as outlined in claim eight, additional comprising: suggests for resetting the suggests for delaying the monotone sign through a reset period of time, whereby the reset period of time is previous to the clock Appraise time period.
In more specific areas of the creation, the method may possibly further include resetting the resettable delay line segments for the duration of a reset period of time.
a first plurality of resettable delay line segments that each delay the initial monotone signal to create a respective initially plurality of delayed monotone alerts, wherein resettable delay line segments concerning a resettable hold off line phase linked to a bare minimum delay time in addition to a resettable hold off line phase connected to a utmost delay time are Every connected to discretely rising delay moments;
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A different aspect of the invention might reside within an apparatus for detecting clock tampering, comprising: suggests 250 for furnishing a monotone sign 220 through a clock Consider period of time 310 linked to a clock CLK; means 210 for delaying the monotone signal employing a plurality of resettable delay line segments to deliver a respective plurality of delayed monotone signals 230 obtaining discretely raising hold off times amongst a minimum hold off time plus a greatest delay time; and usually means 240 for using the clock CLK to cause an Appraise circuit 240 that takes advantage of the plurality of delayed monotone alerts to detect a clock fault.
employing a clock to cause an evaluate circuit that makes use of the plurality of delayed monotone signals to detect a voltage fault.